In the fabrication processes for semiconductor devices, an integrated circuit chip is frequently assembled in a package in a final process step to complete the fabrication process. The assembled package can then be connected to a printed circuit board as part as a large circuit. To establish an electrical communication with the integrated circuit chip, a wire bonding process is frequently used to connect a multiplicity of bond pads on the integrated circuit chip to the outside circuitry.
In a typical IC chip, active circuit elements such as transistors, resistors, etc., are positioned in the central portion, i.e., the active region, of the chip while the bond pads are normally arranged around the periphery of the active region such that active circuit elements are not likely to be damaged during a subsequent bonding process. When a wire bonding process is performed on a bond pad on an IC chip, the process normally entails the bonding of a gold or aluminum wire to the bond pad by fusing the two together with ultrasonic energy. The wire is then pulled away from the bond pad after the bond is formed. During the pulling of the gold wire from the bond, a defect known as bond pad lift-off is frequently encountered. It occurs based on the fact that during the attaching process of a gold wire to a bond pad, a high level of stress is placed on the bond pad. It occurs because a relatively large, heavy bond is placed on top of layers which may not have strong adhesion to the underlying layers. For instance, one factor that affects adhesion between the layers is the common usage of a diffusion barrier layer formed of a material such as TiN for preventing aluminum diffusion into underlying conductive layers during subsequent high temperature processes. The diffusion barrier layer utilized, i.e., TiN, TiW or other alloys, does not have a strong adhesion to the underlying oxide layer in the bond pad. This is only one reason that bond pad lift-off defect occurs. Other reasons such as the high bonding stress and the high pull force also contribute to the lift-off problem. Most lift-off problems occur at an interface between a polycide layer and a field oxide layer.
It is therefore an object of the present invention to provide a bond pad structure that does not have the drawbacks and shortcomings of the conventional bond pad structures used on integrated circuit devices.
It is another object of the present invention to provide a bond pad structure on a semiconductor device that is formed in a chess-board patterned such that bonding stress can be buffered to prevent bond pad lift-off defect from occurring.
It is a further object of the present invention to provide a chess-board patterned bond pad structure that has stress buffered characteristics by first building a multiplicity of bird's beak field oxide regions on a silicon substrate.
It is another further object of the present invention to provide a chess-board patterned bond pad structure on a semiconductor device that has stress buffered characteristics by first building a multiplicity of bird's beak field oxide regions on a silicon substrate, then depositing a conductive material layer on the field oxide regions to form a stepped surface such that bonding stress can be more effectively distributed.
It is still another object of the present invention to provide a chess-board patterned bond pad structure on a semiconductor device that has stress buffered characteristics by first building a multiplicity of bird's beak field oxide regions on a silicon substrate, and then forming a multiplicity of conductive gates on each of the field oxide regions resulting a stepped surface.
It is yet another object of the present invention to provide a chess-board patterned bond pad structure on a semiconductor device that has stress buffered characteristics by first building a multiplicity of bird's beak field oxide regions on a silicon substrate and then forming a multiplicity of polycide gates on each of the field oxide regions resulting in such that, after a metal layer is deposited on top, a stepped surface is formed to more effectively distribute a bonding stress.
It is still another further object of the present invention to provide a method for fabricating a chess-board patterned bond pad structure by first forming a multiplicity of field oxide regions in rows and columns in a surface layer of a silicon substrate and then depositing a conductive material layer on top of the silicon substrate to form a stepped surface prior to the deposition of a metal layer on top.
It is yet another further object of the present invention to provide a method for fabricating a chess-board patterned bond pad structure on a semiconductor device by first forming a multiplicity of bird's beak field oxide regions in the surface of a silicon substrate and then forming a multiplicity of polycide gates on each of the multiplicity of bird's beak field oxide regions prior to the deposition of a metal layer on top.